VLSI Verification Engineer
On-site · Warsaw, Mazovia, Poland or Katowice, Silesia, Poland
Job Summary
Senior VLSI Verification Engineer responsible for developing and executing verification plans for ASIC/SoC components in AI accelerator hardware; build, extend, and maintain UVM-based verification environments (agents, drivers, sequencers, monitors, scoreboards, checkers); apply constrained-random and coverage-driven verification; debug complex hardware and HW/SW interactions; collaborate with RTL designers, architects, and validation teams to drive issues to closure; analyze functional coverage and participate in subsystem and SoC-level verification activities; must have SystemVerilog, UVM, and experience with EDA tools; roles based in Poland with offices in Gdansk, Krakow, Warsaw, and Katowice.
Required Qualifications
- B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field
- Minimum 5 years of hands-on experience in ASIC/SoC verification
- Strong proficiency in SystemVerilog, UVM, and constrained-random verification
- Solid understanding of digital design principles and RTL coding (Verilog/VHDL)
- Experience with EDA simulation and debug tools from Synopsys, Cadence, or Siemens/Mentor
- Proven ability to debug complex digital logic and HW/SW interactions
- Strong analytical mindset, communication skills, and ability to work in multidisciplinary teams
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