VHDL Design Engineer
$170,000–$220,000 year
On-site · Cincinnati, Ohio, United States
Job Summary
VHDL/Verilog Design Engineer role focusing on FPGA/ASIC design and DSP waveform development for SDR hardware. Responsibilities include architecture design, simulation/verification, implementing waveforms/algorithms, DSP and fixed-point considerations, lab/field testing with signal generators and spectrum analyzers, documentation of firmware, development of FPGA/IP cores, and multidisciplinary teamwork. Requirements include a Bachelor's or Master’s degree in Electrical/Computer Engineering (wireless/DSP), proficiency in VHDL or Verilog, DoD-related experience a plus, and eligibility to obtain US security clearance. Travel to customer sites and events is expected; role is onsite in Cincinnati, OH with relocation support for the right candidate.
Required Qualifications
- Bachelor’s degree or Master’s degree in Electrical/Computer Engineering (wireless communications/DSP) or equivalent
- Proficient in VHDL or Verilog
- Experience with FPGA/ASIC architecture design, simulation and verification
- Willingness to obtain United States Security Clearance
- Ability to travel to support events (customer site, proposals) and work onsite in Cincinnati, OH
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