Verification Engineer (f/m/d)
On-site · Edinburgh, Scotland, United Kingdom
Job Summary
Verification Engineer to contribute to the verification of digital and mixed-signal ASIC designs. Role involves developing and executing verification plans, creating testbenches and test cases using SystemVerilog and UVM, running simulations, debugging design issues, collaborating with design and verification teams to align with specifications, documenting results, and contributing to coverage analysis and regression testing. Candidate will learn and apply best practices in design verification and participate in process improvements.
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, ComputerEngineering, or related discipline.
- 2-5 years relevant experience in design or mixed-signal verification.
- Strong understanding of digital logic design.
- Familiarity with HDL languages (SystemVerilog, Verilog, VHDL) and simulation tools.
- Exposure to scripting languages (Python, Perl, Tcl) is a plus.
- Knowledge of SystemVerilog and UVM methodology.
- Exposure to version control systems (Git) and Linux-based development environments.
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