UIUC Research Park Intern - FPGA Design
$52,000–$83,200 year
On-siteChampaign, Illinois, United States
Job Summary
Translate fixed-point mathematical models into optimized RTL modules for camera data processing and write custom SystemVerilog or Verilog code to manage high-throughput data flows. Instantiate and integrate third-party soft IPs into the top-level design, then run functional simulations and static timing analysis to resolve violations. Manage the full FPGA build flow from synthesis to bitstream generation, handle hardware flashing, and collaborate with system software engineers on end-to-end integration. Participate in hardware bring-up, debugging, and continuous integration testing within the autonomous vehicle HIL framework.
Required Qualifications
- Must be currently pursuing a bachelors, masters, or PhD degree at the University of Illinois Urbana Champaign
- Actively pursuing a degree or one closely related in Electrical Engineering, Computer Engineering, or Computer Science
- Hands-on experience with SystemVerilog, Verilog, or VHDL through coursework, academic projects, or internships
- Solid understanding of digital logic design, finite state machines (FSMs), pipelining concepts, fixed-point arithmetic, and basic digital signal/data processing principles
- Familiarity with major FPGA EDA suites (e.g., AMD/Xilinx Vivado, Intel Quartus) and simulation tools (e.g., ModelSim, QuestaSim, Vivado Simulator)
- Basic understanding of common system buses and interfaces (e.g., AXI4, APB, PCIe, Ethernet, SPI, or UART)
- Strong analytical and debugging skills with a willingness to work hands-on with hardware testing equipment (logic analyzers, oscilloscopes)
Desired Qualifications
- Exposure to video/image processing pipelines or camera protocols (e.g., MIPI CSI-2 and GMSL)
- Scripting experience (Python, TCL, or Bash) for automating build flows, simulations, and data analysis
- Basic understanding of C/C++ or embedded software development to better interface with software teams
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