Template Job
$207,000–$230,000 year
On-siteSan Jose, California, United States
Job Summary
Architect and design high-speed analog and mixed-signal circuits including PLLs, LDOs, references, SerDes building blocks, ADCs/DACs, and clocking from specification through schematic, layout supervision, and verification across PVT corners. Lead silicon bring-up, characterization, and debug while partnering with validation and product engineering to root-cause issues and execute test plans correlating performance against targets. Set analog design methodology, review standards, and mentor junior engineers to elevate the technical capability of the analog organization. Drive full-chip solutions through cross-functional collaboration with digital, physical design, systems, and architecture teams.
Required Qualifications
- MS or PhD in Electrical Engineering or a related field
- 8+ years of experience in analog and mixed-signal integrated circuit design
- Proven track record designing high-speed analog circuits such as PLLs, SerDes front-ends, data converters, references, or regulators in advanced CMOS/FinFET nodes
- Strong understanding of physical-layer design principles, signal integrity, and high-speed I/O
- Proficiency with industry-standard design and simulation tools (e.g., Cadence Virtuoso, Spectre) and solid layout/parasitic-aware design skills
Desired Qualifications
- Experience taking multiple analog/mixed-signal designs through full production tape-out and high-volume manufacturing
- Expertise in high-speed serial link design (PCIe, Ethernet, UALink, UCIe) and associated PHY architectures
- Familiarity with silicon debug, ATE test development, and design-for-test techniques
- Experience mentoring engineers and leading technical design reviews
- Excellent communication skills and a collaborative, ownership-driven mindset
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