Technical Staff Engineer-Design Implementation
On-site · Chandler, Arizona, United States
Job Summary
Senior silicon implementation engineer responsible for developing and deploying advanced SoC implementation flows for 12nm silicon, with focus on hierarchical design planning, timing convergence, and multi-die integration. Drives RTL-to-silicon methodology across complex SoC programs, defines top-level timing methodologies across IPs and full-chip integration to ensure predictable signoff targets, and leads implementation strategies including partition-aware RTL, constraints strategy, and integration flows. Mentors engineers on timing closure, design implementation flows, and multi-die best practices, evaluating partitioning impact on timing, power, yield, and scalability. Travel up to 25% is expected.
Required Qualifications
- BS or MS in Electrical Engineering or related field
- 14+ years of experience in SoC implementation activities
- Synthesis, timing closure, hierarchical implementation, and low-power digital design flows
- Understanding of SoC timing architecture including clocking, constraint development, timing budgeting, and block-to-top convergence
- Ability to incorporate system-level timing specifications into implementation constraints
- Experience with multi-die integration and partition-aware RTL development
- Mentor engineers on design implementation flows and timing closure strategies
- Strong cross-functional communication and technical leadership in ambiguous environments
- Experience building new process flows and scaling implementation methodologies
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