Technical Lead Physical Design Engineer
$140,000–$180,000 year
On-siteToronto, Ontario, Canada
Job Summary
Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. Develop and validate SDC constraints, including MMMC setup, to enable accurate STA analysis. Define and manage I/O timing budgets across hierarchical designs while applying advanced sign-off methodologies at TSMC 7nm and below. Leverage ETM libraries for hierarchical timing analysis and correlation, balancing runtime and accuracy. Provide actionable timing feedback at both block and full-chip levels, including root cause analysis and ECO guidance. Manage large-scale multi-corner/multi-mode STA runs with automation and partner closely with design, implementation, and verification teams to drive timing convergence. This role is fully on-site and in-person.
Required Qualifications
- Bachelor's in Electrical Engineering or Computer Science
- ≥5 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications
- Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below)
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains
- Strong scripting ability (Tcl, Python, Perl)
- Ability to work independently with strong prioritization and a professional, customer-focused mindset
Desired Qualifications
- Master's
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis
- Experience working with IP vendors for both RTL and hard-macro integration
- SystemVerilog/Verilog familiarity
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