Technical Lead Design Verification Engineer
$147,000–$195,000 year
On-site · California, United States
Job Summary
Technical Lead Design Verification Engineer responsible for the full verification lifecycle of complex ASICs/SoCs for server, storage, and networking applications. You will act as a code-breaker, designing and implementing verification strategies across planning, test development, and debugging, and collaborating with RTL designers, software, and system validation teams to develop and execute test plans on emulation platforms. Must have strong experience with SystemVerilog, UVM, and C/C++, plus scripting in Python or Perl to automate verification infrastructure. The role emphasizes writing tests, collecting and closing coverage, and identifying verification holes to enable high-quality tape-out. Preferred experience includes working with Verification IPs and protocols such as PCIe (Gen-3 and above), Ethernet, NVMe, DDR4/5, and related tooling. The base salary range is USD 147,000.00 – USD 195,000.00, with final compensation determined by location and experience. We encourage applicants with diverse backgrounds to apply. The posting notes US work authorization and immediate availability.
Required Qualifications
- Bachelor’s in Electrical Engineering (EE)
- ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
- Experience with SystemVerilog/UVM/C/C++
- Proven ability to develop test plans and sequences; generate stimuli; debug failures
- Experience with different verification methodologies and coverage measures; regression systems; familiarity with simulators
- Authorized to work in the US and able to start immediately
- Strong problem-solving, independent work capability, and customer-focused mindset
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