Technical Director, DFT

Lead DFT architecture and methodology development for advanced SoC designs. Drive DFT strategy and planning for new projects, coordinating with design, verification, and physical design teams to integrate DFT solutions into the flow. Manage DFT implementation activities including scan insertion, ATPG, BIST, and boundary scan (JTAG) insertion; perform DFT verification and sign-off with scan chain simulations, fault simulations, and coverage analysis. Collaborate with Test Engineering to enable manufacturing and production test, investigate and resolve DFT issues during silicon bring-up, and guide cross-functional teams to implement effective solutions. Stay current with DFT trends and drive continuous improvement in DFT efficiency. Mentor junior engineers and provide technical leadership in DFT methodologies and best practices. Preferred qualifications include a Master’s degree in Electronics/related field and experience with hierarchical DFT, DFT automation (TCL/Python), and post-silicon DFT activities. Knowledge of IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG), plus tools such as Mentor Tessent, Synopsys DFT Compiler, and Cadence Encounter Test.