Tech Lead Physical Design Engineer, Power Integrity
$160,000–$200,000 year
On-siteSan Jose, California, United States
Job Summary
Own static and dynamic IR drop and electromigration analysis at block and full-chip levels, driving closure to foundry sign-off criteria for Astera Labs' connectivity ASIC portfolio. Partner with power grid, floorplan, and implementation teams to resolve voltage drop hotspots and EM violations early, ensuring stable power delivery from early floorplan through tapeout. Develop EMIR runsets, stimulus methodologies, and automation infrastructure to improve predictability and reduce iterations across multi-corner analysis. Deliver clear root-cause analysis and mitigation guidance while collaborating with RTL, STA, verification, and IP vendors to drive power integrity convergence.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced nodes (7nm and below)
- Deep expertise in power grid design, PDN analysis, and EM reliability mitigation, including static and dynamic IR methodologies and foundry sign-off criteria
- Proficiency with Cadence Voltus and/or Synopsys RedHawk-SC / PrimeTime PX
- Strong scripting ability in Tcl, Python, and/or Perl for flow automation and data analysis
- This role is fully on-site at our San Jose, CA location
Desired Qualifications
- Master's degree in Electrical Engineering or a related field
- Power integrity experience on high-speed SerDes, Ethernet PHY, or PCIe designs
- Package-level power delivery analysis / co-simulation, including advanced packaging or multi-die integration exposure
- Experience building EMIR methodology infrastructure that scales across multiple concurrent tapeout programs
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