Team Lead Verification Engineer
$70,000–$85,000 year
HybridGraz, Styria, Austria
Graz, Styria, AustriaHybridFull Time$70,000–$85,000 yearSenior LevelMasters Degree
Full TimeSenior LevelMasters Degree
Job Summary
Perform functional verification, validation, and debugging of digital designs for mixed-signal ASICs and FPGAs, applying UVM methodologies to develop test plans and drive projects from concept to tape-out. Execute RTL design debugging and implement verification tools while collaborating within a team to ensure seamless transitions from concept to implementation. This full-time hybrid role in Graz offers relocation support, skills analysis, and access to cutting-edge tools like Cocotb for engineers specializing in RISC-V based microcontroller systems for edge computing and AI applications.
Required Qualifications
- A minimum of 8 years of experience in digital verification for ASICs and/or FPGAs (8 years with a Master's degree, 10 years with a Bachelor's degree)
- Skills in Functional Verification and Validation
- Experience in verifying digital designs
- Experience in RTL design debugging
- A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- The ability to work independently and as part of a team
Desired Qualifications
- Experience in working with version control systems (Git preferred)
- Experience in FPGA/ASIC development as a plus
- Experience in verifying digital designs (UVM preferred)
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