Static Timing Analysis (STA) / Timing Closure & Signoff Engineer - San Diego, Santa Clara, CA / Austin, TX (IK)
On-siteSan Diego, California, United States
Job Summary
Develop and maintain timing constraints, including clock definitions, CDC exceptions, and multicycle paths, ensuring consistency across all modes and corners. Perform block-level and full-chip static timing analysis using Synopsys PrimeTime or Cadence Tempus to identify setup, hold, and transition violations. Close timing by generating ECOs and coordinating fixes with place-and-route teams while managing crosstalk, noise, and RC parasitic extraction. Apply OCV, AOCV, and POCV methodologies for variation-aware signoff and build hierarchical timing abstracts for advanced-node designs. Automate analysis flows using TCL, Python, or Perl to improve turnaround time and deliver silicon-ready signoff reports. Collaborate with synthesis, physical design, and DFT teams to validate timing budgets and support clean tapeouts.
Required Qualifications
- Strong fundamentals in static timing analysis — setup/hold, recovery/removal, timing arcs, slack, path groups, clock latency, uncertainty, and derating concepts.
- Hands-on experience with Synopsys PrimeTime / PrimeTime SI for block and/or full-chip timing signoff.
- Proficiency in SDC constraint development, debug, and validation (clocks, I/O timing, exceptions, CDC).
- Experience with MMMC (multi-mode multi-corner) analysis and closure.
- Understanding of OCV / AOCV / POCV variation-aware timing methodologies.
- Working knowledge of crosstalk / signal-integrity analysis and noise closure.
- Familiarity with parasitic extraction and SPEF (StarRC / Quantus QRC) and RC corner concepts.
- Solid understanding of the physical design flow — synthesis, place-and-route, and clock tree synthesis — and its interaction with timing.
- Exposure to advanced technology nodes (16nm / 7nm / 5nm / 3nm FinFET).
- Strong scripting skills in TCL (mandatory).
- Python or Perl for flow automation.
- Good debugging skills, clear communication, and the ability to work in a cross-functional, delivery-driven team.
- Must be able to lift 50 lbs
Desired Qualifications
- Experience with Cadence Tempus / Quantus signoff tools.
- Low-power design exposure — UPF, power domains, level shifters, and isolation cells.
- Hierarchical timing signoff, timing budgeting, and ETM / ILM model generation and validation.
- IR-drop / electromigration awareness and exposure to Ansys RedHawk / Cadence Voltus (rail-aware timing).
- DFT timing knowledge — scan, ATPG, and test-mode (shift/capture) timing closure.
- Formal SDC / constraint verification tools and glitch / dynamic-power awareness.
- Experience across multiple full tapeouts from RTL-to-GDSII signoff perspective.
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