Static Timing Analysis (STA) Engineer
$76,146–$110,334 year
On-site · Toronto, Ontario, Canada
Job Summary
Static Timing Analysis (STA) Engineer responsible for executing timing analysis for FPGA designs, debugging violations, and collaborating with RTL, synthesis, and physical design teams to achieve timing closure. Responsibilities include developing and validating timing constraints, applying STA methodologies, and contributing to flow improvements and automation to optimize performance, power, and area. The role emphasizes cross-functional collaboration to improve timing convergence and requires strong experience with STA fundamentals, industry-standard tools, and RTL design (Verilog/SystemVerilog). Canadian compensation is provided with an estimated salary range and performance-based incentives.
Required Qualifications
- 6+ years experience in Static Timing Analysis (STA) for ASIC or FPGA designs
- Solid understanding of STA fundamentals (setup/hold, timing paths, clocking, CDC basics)
- Experience with industry-standard tools (e.g., PrimeTime or equivalent)
- Familiarity with synthesis and place & route flows
- Working knowledge of RTL design (Verilog/SystemVerilog) for FPGA or ASIC design methodologies
- Debug & problem-solving skills to analyze timing reports and propose actionable solutions
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
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