Static Timing Analysis Engineer
Hybrid · Bengaluru, Karnataka, India
Job Summary
Perform timing analysis and optimization to ensure design functionality and performance at the chip and block levels. Generate and verify timing constraints, address and resolve timing violations during SoC development. Conduct timing rollups, develop and implement power-optimized clock networks, and ensure alignment with high-performance, low-power guidelines. Define and implement methodologies to deliver quality timing models that enhance the efficiency of the physical design process. Set process, voltage, and temperature (PVT) conditions for timing analysis based on product plans and operating conditions. Collaborate with architecture, clock design, logic design, and backend teams to achieve clocking balance, power delivery optimization, and efficient partitioning. Partner with the clocking team to refine methodologies and validate integration flows for chip-level timing solutions.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in Physical Design with a Bachelor's degree, 6+ years with a Master's degree, or 4+ years with a PhD
- Proficiency in static timing analysis tools and methodologies
- Demonstrated expertise in timing modeling, verification, constraint generation, and optimization techniques
- Technical understanding of PVT conditions and their application in timing analysis
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.