Staff VLSI Design Engineering (SOC Verification, System Verilog, UVM)with 8 to 12 years of experience
On-siteBengaluru, Karnataka, India
Job Summary
Lead functional verification closure for complex IP blocks and full-chip SoC designs by developing comprehensive test plans, verification strategies, and UVM-based environments. Create reusable verification components, including bus functional models, monitors, and checkers, while driving coverage-driven validation and sign-off. Develop System Verilog Assertions and optimize automation tools to enhance productivity. Collaborate with design architects, RTL designers, and post-silicon teams to ensure seamless integration, and investigate root causes for design failures. Mentor junior engineers and contribute to continuous improvement of verification methodologies. Bring AI/ML and automation-based initiatives to the team.
Required Qualifications
- 7 to 11 years of relevant experience in VLSI design verification
- Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering
- Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
- Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
- Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
- Proven ability to lead technical projects and manage stakeholder relationships effectively
- Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules
Desired Qualifications
- Master's degree preferred
- Experience with NAND flash memory protocols and memory design verification
- Track record of mentoring junior engineers and contributing to process improvements
- Experience with formal verification methodologies and assertion-based verification
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