Staff SoC RTL Engineer
$175,000–$230,000 year
On-siteBurlingame, California, United States
Burlingame, California, United StatesOn-siteFull Time$175,000–$230,000 yearSenior LevelDoctorate Or Professional DegreeSmall
Full TimeSenior LevelDoctorate Or Professional DegreeSmall
Job Summary
Own SoC-level subsystem development and integrate third-party IP such as NoC, PCIe/UCIe interfaces, DDR, and Security. Contribute to SoC architecture definition by deeply understanding application requirements and drive Power, Performance, and Area (PPA) optimization strategies using low-power digital design techniques. Apply timing closure across the full product lifecycle from front-end to tapeout, balancing single-stream latency against scaled throughput. Independently deliver design releases for customer evaluation and integration within the first year.
Required Qualifications
- BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field
- Minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience
- Proficiency in SystemVerilog or Verilog
- Strong background in computer architecture, low-power digital design techniques, and deep technical knowledge in at least one subsystem (Memory, I/O, or Compute)
- Proven experience with SoC subsystems (including 3rd-party IP) and working knowledge of VCS & Verilog/C Co-Simulation
Desired Qualifications
- Experience in logic synthesis and performance modeling
- Experience in FPGA design
- Familiarity with automotive safety standards (ASIL) and hardware security standards
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