Staff RTL Design Engineer - CPU LS/PF/MMU
$178,848–$218,592 year
On-siteAustin, Texas, United States or Santa Clara, California, United States
Job Summary
Architect, design, and implement new features, performance improvements, and ISA extensions in RISC-V CPU core generators using Chisel. Integrate design content into the Chisel/FIRRTL framework to enable automatic configuration, documentation generation, and verification testbenches. Perform initial sandbox verification, collaborate with the verification team to create test plans, and work with the physical implementation team to optimize frequency, area, and power goals. Partner with the performance modeling team for exploration and optimization while ensuring knowledge sharing through comprehensive documentation. This role supports SiFive's mission to transform compute by bringing RISC-V to high-performance applications in AI, automotive, and data centers.
Required Qualifications
- BS/MS degree in computer science, computer engineering, electrical engineering or related field, or equivalent experience
- 3+ years of design experience
- Academic or professional experience with CPU RTL design
- Proficiency in hardware (RTL) design in Verilog, System Verilog, or VHDL
- Strong software engineering skills/background, including: Object-oriented, aspect-oriented, and particularly functional programming
- Test-driven development, particularly ability to write adaptive unit tests
- Attention to detail and a focus on high-quality design
- Good verification principles, SVA, and coverage
- Ability to work well with others and share the belief that engineering is teamwork
- Successful background and reference checks
- Satisfactory proof of your right to work in United States of America
- Authorized for access to export-controlled technology under applicable export control laws
Desired Qualifications
- Experience with Scala/Chisel, Bluespec, or some other language/DSL for generating configurable hardware via software
- Knowledge of RISC-V instruction set architecture
- Expertise in out-of-order processor micro-architecture, design, and verification in one or more of the following areas: load-store unit, coherent caches, cache prefetching, virtual memory MMU/TLBs
- Familiarity with Git/Github, Jira, Confluence
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.