Staff Physical Design Engineer

Senior Physical Design Engineer responsible for implementing digital blocks in advanced tech nodes, driving timing closure, power integrity, and physical verification for high-performance ASICs. Role involves understanding and debugging timing constraints, derates and margins; reviewing signoff STA reports; building and customizing power grids; clock implementation for functional/test clocks; debugging DRC/LVS; functional and timing ECOs; manual layouts and silicon photonics layout; collaborating with EDA vendors to resolve tool issues; and scripting (TCL, Python, Shell) to automate or customize flows. Preferred qualifications include a Master’s degree and Cadence tool experience. The role requires strong teamwork across multiple functional teams in a fast-paced environment and offers a flexible hybrid workplace.