Staff Memory Design Engineer, DRAM
On-site · Boise, Idaho, United States
Boise, Idaho, United StatesOn-siteFull TimeMid LevelBachelors DegreeEnterprise
Type
Full Time
Level
Mid Level
Education
Bachelors Degree
Company size
Enterprise
Job Summary
In this role, you will design and analyze digital and analog circuits for next‐generation memory products. Responsibilities include modeling parasitics, guiding physical layout, and performing simulations using industry tools. Collaboration with global teams is essential to enhance product performance and reliability. Candidates should have significant experience in DRAM design and strong technical skills in circuit design and verification.
Required Qualifications
- BS or MS in Electrical Engineering or related field
- 6 years of experience in DRAM design, product, or system
- Coursework in CMOS circuit design, VLSI, and digital circuit design
- Experience with Cadence Virtuoso
- Understanding of physical layout, circuit floor planning, and device reliability
- Experience using FINESIM, HSPICE, and VERILOG
Desired Qualifications
- Strong problem‐solving skills with curiosity for new approaches
- Deep knowledge of industry‐specific technologies and trends
- Excellent communication and collaboration skills
- Expertise in DRAM subsystem architecture, specification, operation, or design
Additional Requirements
- All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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