Staff Memory Design Engineer, DRAM
On-site · Boise, Idaho, United States
Boise, Idaho, United StatesOn-siteFull TimeMid LevelBachelors DegreeEnterprise
Type
Full Time
Level
Mid Level
Education
Bachelors Degree
Company size
Enterprise
Job Summary
Design, optimize, and validate memory, logic, and analog circuits for next-generation DRAM; model parasitics and support design validation, reticle experiments, and tape-out revisions; guide and manage physical layout including floor-planning, placement, and routing; perform modeling and simulation using industry-standard tools; collaborate across teams to improve design quality and ensure manufacturable solutions.
Required Qualifications
- BS or MS in Electrical Engineering or related field plus 6 years of experience in DRAM design, product, or system
- Coursework in CMOS circuit design, VLSI, and digital circuit design
- Experience with Cadence Virtuoso
- Understanding of physical layout, circuit floor planning, and device reliability
- Experience using FINESIM, HSPICE, and VERILOG
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