Staff IO Design Engineer

Staff/Sr. Staff IO Design Engineer position within Microchip's Data Center Solutions unit. Responsibilities include design planning of pad rings and package substrates, dynamically defining and optimizing pad ring connectivity, interfacing with cross-functional teams on deliverables (DEF, Verilog netlist, etc.), supporting JTAG TAP controller integration and IEEE 1149.1 compliance across SoC designs, collaborating on TAP controller operation and post-silicon debug, and assisting with verification, emulation, and lab validation including debug and workaround development. Required experience includes B.S or M.S in electrical engineering with 12+ years, IO planning and implementation, IO cell placement, IO standards, SerDes/DDR/PCIe/CXL interfaces, Verilog/SystemVerilog, JTAG/Boundary Scan, DFT methodologies, and strong communication and documentation skills. Travel time 0% - 25%.