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AndurilPosted 1 month ago

Staff FPGA Engineer, EW

$220,000–$292,000 year

On-siteCosta Mesa, California, United States

Full TimeSenior LevelLargeDefense Technology

Job Summary

Own FPGA development for various software defined radio platforms that enable EW functions and work with software and electrical engineers to bring up state of the art boards. Design and test VHDL DSP modules and infrastructure, integrating subsystems into larger FPGA cores while solving resource and timing contentions. Develop drivers for custom RF component boards including PLLs and mixed signal front ends, and manage project deliverables against timeline with effective documentation. Requires strong experience with DSP implementation, Xilinx/AMD SOC/FPGAs, HDL design using VHDL and Verilog, and Linux development environments. Must be eligible for a U.S. Secret security clearance and have experience mentoring engineers.

Required Qualifications

  • Strong experience with DSP implementation for embedded devices and/or software defined radios
  • Experience with Xilinx/AMD SOC/FPGAs; knowledgable of architecture
  • Experience with bring-up of high speed digital interfaces (PCIE, JESD, Aurora, N-Gbps Optical, etc)
  • Proficient in HDL design using VHDL and/or Verilog
  • Proficiency in a Linux development environment
  • Proficiency using Git and CI/CD workflows (Git, TCL, CI/HITL)
  • Eligible to obtain and maintain an active U.S. Secret security clearance
  • Experience mentoring/leading 1-3 engineers through larger design tasks
  • You are a self starter, outcome driven, and an excellent communicator

Desired Qualifications

  • Experience working with the latest AMD SOC/FPGAs
  • Knowledge of AMD FPGA NOC and advanced design features (partial reconfiguration, DFX, segmented flow, ...)
  • Working knowledge of signal processing flows (data converter to bits)
  • Exposure to wireless communications and/or radar systems design
  • Experience with RF test equipment (Spec An, Sig Gens, Oscilloscope, etc)
  • Knowledge or experience using AMD AIE tiles for processing

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