Staff Engineer, VLSI Design Engineering (SOC Verification, UVM) with 8 to 12 years of experience
On-siteBengaluru, Karnataka, India
Job Summary
Lead the development and execution of comprehensive test plans, verification strategies, and verification infrastructure for complex IP blocks, sub-systems, and SoC designs. Design and implement verification environments using industry-standard UVM frameworks, develop reusable components including bus functional models, monitors, and checkers, and drive functional coverage-driven verification closure. Create and optimize verification automation tools, develop System Verilog Assertions, and investigate design failures through root-cause analysis with cross-functional teams. Mentor junior engineers and contribute to continuous improvement of verification methodologies. Bring AI/ML/Automation based initiatives to enhance productivity. Requires 8 to 12 years of experience, a B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering, and advanced proficiency in C, Verilog, SystemVerilog, and UVM.
Required Qualifications
- 8 to 12 years of relevant experience
- B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
- Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering
- Advanced proficiency in C, Verilog, SystemVerilog, and UVM (Universal Verification Methodology)
- Hands-on experience with industry-standard verification tools including Xcellium, Verdi, and JasperGold formal verification tools
- Demonstrated expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off
- Proven ability to lead technical projects and manage stakeholder relationships effectively
- Excellent written and verbal communication skills with demonstrated ability to adapt to dynamic project requirements and deliver results under challenging schedules
Desired Qualifications
- Master's degree preferred
- Experience with NAND flash memory protocols and memory design verification
- Track record of mentoring junior engineers and contributing to process improvements
- Experience with formal verification methodologies and assertion-based verification
- Tools experience/exposure: Xcelium simulator, Verdi Debugger, Jaspergold Formal, Vmanager Regression manager
- Relevant end to end Verification tools exposure from leading EDA vendors
- Bring in AI/ML/Automation based initiatives
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