Staff Engineer, VLSI Design Engineering(Logic Design)

Job Summary

Required Qualifications

• MSEE plus 5 years of relevant experience
• Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design
• Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification)
• Working knowledge of NAND flash memory cell device operations, algorithms for program/read/erase
• Excellent communication (written and verbal) and interpersonal skills

Desired Qualifications

• Experience developing digital circuit designs for low power operating conditions
• Working knowledge of device physics and process
• Working knowledge of NAND Flash memory design including Analog, Core, Datapath and IO circuits
• Proficiency with following Digital design tools Synthesis - Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler
• Static Timing - Synopsys Primetime or Cadence Tempus
• Place and Route - Synopsys ICC or Cadence Encounter or Innovus
• Familiarity with revision control tool and EDA standard formats used in cell/library development and modeling - Liberty (timing model), SDC (Synopsys Design Constraints)
• Programming experience in C, C++, Python or Perl