Staff Engineer, STA and Synthesis

STA Engineer is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. Own timing constraint development and validation, perform setup/hold and variation-aware analysis, and partner with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout. Responsibilities include performing full-chip and block-level Static Timing Analysis (STA) across all modes and corners; analyzing and debugging setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations; developing and maintaining timing constraints (SDC creation, validation, and signoff readiness); driving timing closure through ECO implementation and timing optimization; analyzing timing impact due to process, voltage, and temperature variations; supporting timing signoff for pre-layout and post-layout stages; performing cross-functional reviews for timing convergence and providing recommendations; generating timing reports and communicating closure status to project stakeholders. 7–10 years of experience in STA and timing closure for block and/or full-chip designs; strong CMOS fundamentals, timing concepts, and semiconductor design flow; hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts; good understanding of clock tree, clock uncertainty, latency, skew, and jitter; experience in timing constraints development and debugging; strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis; familiarity with timing closure techniques and ECO methodologies; hands-on experience with Synopsys PrimeTime or Cadence Tempus; scripting skills in Tcl, Perl, or Python; ability to analyze and resolve timing violations independently. Nice to have exposure to low-power timing analysis (UPF/CPF), SI-aware timing, Crosstalk analysis, IR-drop-aware timing closure, knowledge of advanced technology nodes and variation-aware signoff methodologies, and exposure to automation/flow development; experience in cross-functional collaboration with PD, RTL, and Signoff teams. Renesas emphasizes a diverse, flexible, and inclusive work environment with remote work options and a focus on innovation and impact.