Staff Engineer – SoC Design Verification

Staff Design Verification Engineer leading verification strategy for complex digital and mixed-signal designs using SystemVerilog and UVM. Architect sophisticated verification environments, mentor junior engineers, and collaborate across teams to ensure product quality and reliability. Role involves post-silicon validation, acting as a principal customer contact on projects, and influencing verification methodology adoption. Must have expert SystemVerilog and UVM, strong test planning, coverage closure, debugging across RTL and gate-level simulations, and experience with EDA tools (Cadence/Synopsys). Preferred MS/PhD in Electrical or Computer Engineering with 7-10+ years of relevant digital design verification experience; travel up to 10%. Location: Bangalore, India.