Staff Engineer, Physical Design - Caches
On-site · Bengaluru, Karnataka, India
Job Summary
Staff Physical Design Engineer (Caches/Memory Subsystems) will own the physical implementation of high-performance cache blocks and tightly integrated SRAM subsystems from RTL to GDSII. You will drive synthesis, place & route, and signoff, participate in cross-abstraction-layer co-design with architecture/RTL/implementation teams, tackle memory-specific challenges such as dense SRAM macro placement and complex routing over macros, and optimize for aggressive power, performance, and area goals. Collaboration with RTL designers, IP vendors, and power teams to ensure efficient integration of memory instances, plus contributing to memory-heavy block methodologies and design flows. Required: 7+ years in physical design of PPA-critical blocks, RTL to GDSI flow experience with Synopsys/Cadence tools, and a Bachelor’s or Master’s in Electrical or Computer Engineering. Education level corresponds to a Master’s degree, with emphasis on memory architectures and cross-disciplinary design expertise.
Required Qualifications
- 7+ years of hands-on experience in physical design implementation of PPA critical blocks (CPUs, Caches etc.)
- Cross-Abstraction Awareness: understand digital logic design and memory architecture
- Ability to read RTL and collaborate with front-end teams
- Proven ability to optimize for aggressive PPA targets using standard physical design techniques
- Hands-on knowledge of RTL to GDS implementation with Synopsys and/or Cadence in synthesis, Place & Route (PnR), and signoff
- Bachelor’s or Master’s in Electrical or Computer Engineering
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