Staff Engineer, IP Dev Layout
On-siteHyderabad, Telangana, India
Job Summary
Design and develop critical analog, mixed-signal, custom digital blocks and full chip-level integration support. Perform layout verification including LVS, DRC, and antenna checks, while ensuring on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership in planning, scheduling, and execution across multiple project environments, communicating effectively with global engineering teams. Create high-quality layouts for critical blocks such as PLL, ADC, DAC, and LDOs using advanced CMOS processes, leveraging expertise in Cadence VLE/VXL and Mentor Calibre. Apply problem-solving skills to physical verification and explore AI-related tools for day-to-day tasks.
Required Qualifications
- 8 to 15 years' experience in analog/custom layout build in advanced CMOS process, in various technology nodes (Planar, FinFET)
- Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS
- Hands on experience in creating layout of critical blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier
- Good understanding of Analog Layout fundamentals (e.g., Matching, Electro-migration, Latch-up, coupling, crosstalk, IR-drop, active and passive static device parasitics)
- Understanding layout effects on the circuit such as speed, capacitance, power and area
- Ability to understand build constraints and implement high-quality layouts
- Ability to understand build hierarchy and different architectures for Memory designs
- Excellent problem-solving skills in physical verification of custom layout
- Multiple Tape out support experience
- Excellent verbal and written communication skills
- BE or MTech in Electronic/VLSI Engineering
Desired Qualifications
- Proactive in exploring and using AI-related tools in day-to-day tasks
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