Staff Engineer, HBM Verification Architecture
On-siteRichardson, Texas, United States
Job Summary
Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, developing turnkey solutions for future HBM designs based on customer and architecture look-ahead information. Drive co-verification through direct customer interactions while mentoring early-career engineers to strengthen team capability and technical growth. Build verification methodology improvements and GenAI applications aligned with HBM design cycles to improve schedules, quality, and capability. Debug and identify root causes for pre-silicon and post-silicon issues in current HBM products, leveraging AI to accelerate analysis, and explore new architectures through sophisticated feasibility analyses.
Required Qualifications
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or related field
- 7+ years of relevant verification engineering experience
- Over 5 years in digital (Verilog), analog (FastSpice), or mixed-signal verification (co-sims or real number modeling)
- Over 4 years working in custom design verification (schematic-based) or RTL design verification flows
- Demonstrated ability to independently define and drive verification strategies for sophisticated projects
- Strong verbal and written communication skills
Desired Qualifications
- Master's in Electrical Engineering, Computer Engineering, or related field, or equivalent experience, accompanied by more than 9 years in verification engineering roles
- One or more patents, trade secrets, or publications showcasing innovation and problem-solving in verification solutions
- Over 4 years in memory products using JEDEC specifications (preferably HBM), with hands-on experience building or reworking verification flows from scratch
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