Staff Engineer, Digital Design Engineering
On-site · Shanghai, Shanghai, China
Job Summary
Staff Digital Design Engineer leads RTL digital design for complex blocks and subsystems, executing full digital design flow including synthesis and timing closure. Collaborates with DFT teams to integrate scan and test features, supports place-and-route activities and ECO implementation, and partners with physical design teams to resolve layout-dependent timing and power issues. Participates in design reviews, contributes to methodology improvements, documents design specifications and results, and works with global, cross-functional teams to influence product quality and execution on high-impact programs.
Required Qualifications
- Strong expertise in digital circuit design and RTL development (Verilog/SystemVerilog)
- Experience with digital design flows: synthesis, STA, and physical implementation
- Experience with Cadence Genus for synthesis
- Experience with place-and-route using Cadence Innovus
- Working knowledge of DFT concepts and implementation tradeoffs
- Ability to collaborate across global, cross-functional teams
- Strong English written and verbal communication skills
- Experience mentoring junior engineers or leading technical initiatives
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