Staff Engineer, Design For Test
On-siteHyderabad, Telangana, India
Job Summary
Execute DFT insertion flows for assigned IP blocks or SoC partitions using Siemens Tessent or Synopsys TestMax, including scan, MBIST, and IJTAG insertion. Run ATPG pattern generation and simulation (SAF/TDF) to validate coverage closure and resolve failures. Perform DFT design rule checking, LEC equivalence checking, and simulation-based validation for assigned partitions. Contribute to scan chain optimization, test data volume analysis, and compression ratio tuning. Support post-silicon bring-up and ATE debug activities for scan, MBIST, and JTAG/IJTAG on hardware. Develop DFT scripts and contribute to automation improvements under direction of senior team members. Document implementation details, coverage results, and debug findings per team standards. Collaborate with Physical Design and timing teams on DFT implementation constraints.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 4–7 years of DFT experience
- Working knowledge of DFT concepts: scan, MBIST, JTAG/IJTAG, ATPG (SAF/TDF), and basic compression/EDT
- Hands-on experience with Siemens Tessent (Modus, Shell) and/or Synopsys TestMax (DFT Compiler, TetraMAX)
- Experience running DFT flows in an RTL or gate-level environment with Synopsys VCS or Cadence Xcelium for simulation
- Basic familiarity with LEC tools (Cadence Conformal or Synopsys Formality) for design equivalence checking
- Good problem-solving skills and the ability to debug DFT insertion and ATPG issues with support from senior engineers
- Familiarity with Linux environment, Tcl/Perl/Python scripting for DFT automation tasks
- Strong communication and teamwork skills; ability to collaborate across global multi-site teams
- Eligible to access export-controlled information as defined under applicable law
Desired Qualifications
- Experience with Siemens Tessent (Modus, Shell)
- Experience with Synopsys TestMax (DFT Compiler, TetraMAX)
- Experience running DFT flows in an RTL or gate-level environment with Synopsys VCS
- Experience running DFT flows in an RTL or gate-level environment with Cadence Xcelium
- Basic familiarity with Cadence Conformal
- Basic familiarity with Synopsys Formality
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