Staff Engineer - ASIC Verification
$145,000–$286,000 year
On-site · San Jose, California, United States or Folsom, California, United States
Job Summary
Staff ASIC Design Verification Engineer responsible for architecture and development of advanced verification environments for complex SoCs; hands-on development of test benches, verification plans, and coverage definitions; collaborate with architecture, firmware, and design teams to debug and resolve critical issues, with focus on System-Verilog/UVM-based verification and familiarity with DDR, PCIe/NVMe or NAND interfaces; strong emphasis on RTL debugging, code coverage, and test-plan execution within a team-oriented, engineering-driven environment.
Required Qualifications
- B.S. in electrical engineering, computer science or equivalent with extensive industry experience
- 6-8 years of deep verification exposure
- Experience with RTL debugging, score boarding and code coverage analysis
- Proven expertise with writing and tracking detailed test-plans at all levels
Desired Qualifications
- SystemVerilog
- UVM
- DDR
- PCIe/NVMe
- NAND
- verification environments
- test benches
- verification plans
- coverage definitions
- RTL debugging
- scoreboarding
- C
- emulation
- gen-AI tools experience (Claude-Code)
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