Staff Engineer, ASIC STA
On-site · Hyderabad, Telangana, India
Hyderabad, Telangana, IndiaOn-siteFull TimeSenior LevelNot SpecifiedEnterprise
Type
Full Time
Level
Senior Level
Education
Not Specified
Company size
Enterprise
Job Summary
Staff Engineer, ASIC STA responsibilities include block/chip tile synthesis for SOC, timing closure, constraint generation, low power verification, RTL analysis, and collaboration with Design/DFT/IP teams. Proficiency with Synopsys/Cadence tools, PnR, formal verification, and scripting in Perl/TCL/Python is expected. The role involves working on processors, controller architectures or ASICs for Enterprise SSD, with emphasis on low-power design, timing budgets, and verification coordination.
Required Qualifications
- 8-14 years of relevant experience in Synthesis/STA
- Good understanding of overall design Flow RTL to GDS
- Hands on Experience on Constraints Generation, timing closure of full chip on Hierarchical Designs
- Hand on Synthesis & STA Experience on Lower node Technologies with Synopsys/Cadence Tools
- Hands on Experience on Equivalent Checks with Synopsys / Cadence Tools
- Good knowledge on Timing Budgets
- Knowledge on Perl / TCL / Python scripting language
- Experience on multi voltage designs using CPF/UPF
- Hands on experience on power analysis using PTPX
- Good understanding of VHDL / Verilog Constructs
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