Staff Engineer, ASIC Physical Design
On-site · Bengaluru, Karnataka, India
Job Summary
Role involves physical design implementation for Enterprise SSD ASICs, focusing on block-level floorplanning, placement, clock tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC and tapeout activities. Requires 8+ years of hands-on physical design experience, APR flow development and PPA analysis, and proficiency with Cadence tools (Innovus, Tempus) and physical verification (Caliber). Strong fundamentals in digital electronics and microprocessors, plus good analytical, ownership, and time-management skills. Bachelor's or Master's degree in electronics or computer architecture. Located in Bengaluru, India. Preferred skills include Cadence PnR tools, formal verification experience, and additional digital-electronics/microprocessor expertise.
Required Qualifications
- Minimum of 8 years of hands-on physical design implementation experience
- Experience with APR flow development and PPA analysis
- Experience with Cadence layout tools (Innovus, Tempus)
- Hands-on experience in Physical verification closure (DRC/LVS/Antenna) with Caliber
- Experience in closing IR issues within the block based on feedback
- Strong fundamentals in digital electronics and microprocessors
- Excellent English and collaboration skills
- Bachelor’s or Masters in electronics/computer architecture
- Preferred skills include Cadence PnR tools, formal verification, and microprocessors experience
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