Staff Engineer, ASIC Physical Design
On-site · Hyderabad, Telangana, India
Job Summary
Role involves physical design for ASICs in the Enterprise SSD Group, including block-level low-power floorplanning, placement, clock-tree synthesis, routing, RC extraction, STA timing closure, IR/EM analysis, DRC/LVS/ERC, and tape-out activities. Proficiency with Cadence tools (Innovus, Tempus) and Caliber for physical verification, plus experience closing IR issues and delivering robust PPA. Requires 8+ years in physical design, familiarity with advanced process nodes (5nm/3nm preferred), strong digital electronics and microprocessor fundamentals, and excellent communication and collaboration. Bachelor's or Master's degree in electronics/computer architecture.
Required Qualifications
- Minimum 8 years hands-on physical design implementation experience
- APR flow development and PPA analysis
- STA closure at block level
- Experience with advanced process technology nodes (5nm/3nm preferred)
- Cadence layout tools (Innovus, Tempus)
- Physical verification closure (DRC/LVS/Antenna) with Caliber
- IR issue resolution within the block
- Strong fundamentals in digital electronics and microprocessors
- Good analytical and problem-solving skills
- English proficiency and collaboration skills
- Bachelor’s or Master’s degree in electronics/computer architecture or related field
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