Staff Engineer, ASIC Design Verification
On-site · Hyderabad, Telangana, India
Job Summary
Staff Engineer for ASIC Design Verification focused on developing verification components for complex SOC designs. Responsibilities include creating new simulation environments, executing verification plans in collaboration with design teams, and debugging complex issues. Must be proficient in constrained random verification and achieving functional coverage closure, with expert-level UVM-based SystemVerilog test-benches and knowledge of verification methodologies, flows, and quality metrics. Requires strong analytical and problem-solving abilities, and good verbal/written communication; team-oriented with interpersonal skills. Education typical requirements include a B.S. in electrical engineering or computer science with extensive industry experience.
Required Qualifications
- B.S. in electrical engineering or computer science
- 3+ years of experience in NAND, DDR and PCIe verification
- expert level with UVM and SystemVerilog
- experience with ASIC simulation tools and advanced verification methods
- experience in writing block-level and SoC test-plans
- strong debugging and problem-solving skills
- excellent communication skills
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