Staff Engineer AI/ML
$106,000–$205,000 year
On-site · Santa Clara, California, United States
Job Summary
Define, lead RTL development of AI-enabled RISC-V CPU core. Responsible for all aspects of design including functional features, performance, power, and area. Drive micro-architecture and design of critical blocks of the CPU core, design of RISC-V Vector CPU core and its custom extensions, and design of an AI-enabled matrix engine to augment the Vector CPU. Explore high-performance strategies with the CPU modeling team. Perform microarchitecture development and specification from early high-level exploration to detailed specs. Configure design features, development, assessment, and refinement of RTL to meet power, performance, area, and timing goals. Perform functional verification support and assist in the design verification strategy. Assist with verification of RTL design performance goals. Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power. Also perform all activities in a safe, environmentally responsible manner and support EH&S requirements.
Required Qualifications
- Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
- Thorough knowledge of microprocessor architecture including expertise in instruction fetch and decode, branch prediction techniques
- instruction scheduling, register renaming, Reorder Buffer (ROB)
- Out-of-order execution
- Integer and Floating-point execution
- Load/Store execution
- Instruction and Data Prefetch
- Vector data path
- Cache and memory subsystems
- Knowledge of Cache coherency and memory consistency
- Knowledge of System Verilog, Verilog and/or VHDL
- Experience with simulators and waveform debugging tools
- Master’s with 4-7 years of experience, PhD 2-5 years of work experience
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