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Silabs5 days ago

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration

$143,150–$265,850 year

Hybrid · Austin, Texas, United States

Type
Full Time
Level
Senior Level
Education
Masters Degree
Company size
Large

Job Summary

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration in Austin, TX role focused on developing highly integrated, low-power SoCs for IoT applications. Responsibilities include architecting and implementing low-power SoC architectures with multiple processors and clock domains, defining UPF/CPF-based power intent, integrating clocking infrastructure and power-management controllers, leading RTL design and integration, validating designs through silicon bring-up, and collaborating across teams to optimize performance, power, and area. The role requires leadership of small design teams, expertise in Verilog/SystemVerilog, experience with AXI/AHB/APB interconnects, clocking, CDC/RDC, and power-aware verification, and proficiency with scripting and common EDA tools. Benefits include a competitive salary, RSUs, 401k, health plans, and a hybrid on-site/remote work arrangement. The position is based in Austin, Texas, USA, with a hybrid work model.

Required Qualifications

  • BS/MS in Electrical Engineering
  • 10-20 years of professional experience in digital CMOS IC design
  • Strong RTL design expertise using Verilog/SystemVerilog
  • Extensive experience with low-power design methodologies (UPF, power gating, retention, isolation, level shifting)
  • Knowledge of embedded processor systems and C coding
  • Experience with industry-standard on-chip bus protocols (AXI, AHB, APB) and interconnect architectures
  • Experience integrating complex subsystems, processor clusters, memory subsystems, and third-party IPs into large SoCs
  • Experience with logic simulators, design/waveform browsers, power analysis tools, and timing constraints
  • Experience with scripting languages (Python, Perl, Tcl) and version control systems (Git, Perforce, Methodics)
  • Excellent written and verbal communication skills
  • Demonstrated ability to lead small teams and drive RTL development, integration, and silicon bring-up
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$143k – $266k / yr

Staff Digital Design Engineer – SOC Low Power, Clocking & Integration · Silabs

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