Staff Design Verification Engineer – SoC and eFPGA
$150,978–$218,624 year
On-siteSan Jose, California, United States
Job Summary
Partner with architecture, RTL, firmware, and software teams to define comprehensive verification strategies and develop detailed plans covering feature interactions and system-level behavior. Design, implement, and maintain directed and constrained-random verification environments and test suites, while developing SystemVerilog assertions and functional coverage models. Debug simulation failures, analyze coverage metrics, and build end-to-end verification flows for eFPGA soft logic within SoCs, including RTL simulation, synthesis validation, and bitstream generation. Contribute to methodology improvements, automation, and continuous integration workflows. This role supports the Embedded FPGA team's innovation in heterogeneous processing and high-performance edge computing solutions.
Required Qualifications
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent industry experience
- Strong understanding of SoC architectures and industry-standard bus protocols such as AXI and AHB
- Experience debugging RTL and firmware using simulation and waveform analysis tools
- Hands-on experience developing UVM-based verification environments
- Proficiency in SystemVerilog, Verilog, C/C++, and Python
- Experience developing automation solutions and working within distributed compute environments
- Working knowledge of SystemC and Transaction-Level Modeling (TLM)
- Strong communication and collaboration skills, with the ability to work effectively across multidisciplinary teams
- Solid understanding of digital design fundamentals, computer architecture, timing analysis, power analysis, process variation, and reliability considerations
- Yes, 10% of the time (travel)
- 1st Shift/Days (shift type)
Desired Qualifications
- 5+ years of experience in SoC, subsystem, or microarchitecture verification
- Experience supporting successful silicon tape-outs in advanced process nodes (N4, N5, or similar technologies)
- Knowledge of Functional Safety (FuSA) requirements and safety-focused hardware verification methodologies
- Experience with FPGA or programmable logic architectures
- Familiarity with continuous integration, regression automation, and verification productivity tools
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