Staff BIOS/Platform System Engineer
$140,000–$220,000 year
On-site · San Jose, California, United States
Job Summary
Senior BIOS Engineer to lead BIOS/UEFI firmware bring-up and validation across AMD/Intel/ARM platforms, focusing on DDR5 memory subsystems, troubleshooting hardware-software interfaces, and developing validation test plans for BIOS features including ACPI, Secure Boot, TPM, and system boot flows. Responsibilities include debug using JTAG, analyzing POST failures, memory training, PCIe enumeration, collaborating with systems engineers, and producing technical docs. Requires a Bachelor’s degree in Electrical/Computer Engineering or Computer Science and 3+ years BIOS/UEFI experience; proficient in C/C++, Python/Bash; experience with UEFI/EDK2, DDR5, SPD/XMP, RAS, JEDEC; familiarity with JTAG, logic analyzers; strong communication.
Required Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field
- 3+ years of hands-on BIOS/UEFI firmware development or validation
- Demonstrated experience with at least two CPU architectures: AMD (AGESA, EPYC/Ryzen), Intel (FSP, Core/Xeon), or ARM (TF-A, EDK2)
- Strong understanding of DDR5 memory architecture, training algorithms, SPD/MR registers, and RAS features
- Proficiency in C/C++ and scripting languages (Python, Bash) for firmware development and automation
- Experience with UEFI/EDK2 framework, SMM, DXE, PEI driver development, and ACPI/ASL
- Familiarity with hardware debug tools: JTAG debuggers, protocol analyzers, oscilloscopes, and serial console interfaces
- Solid understanding of platform busses and interfaces: PCIe, USB, I2C/SMBus, SPI, LPC, UART, and GPIO
- Experience reading and interpreting hardware schematics, datasheets, and silicon vendor documentation
- Excellent analytical and problem-solving skills with the ability to work across hardware and software boundaries
- Strong written and verbal communication skills; experience authoring technical documentation
- Preferred Qualifications: Experience with AMD PSP, Intel ME/CSME, or ARM TrustZone security subsystems
- Familiarity with BMC firmware (OpenBMC) and IPMI/Redfish management interfaces
- Knowledge of server platform RAS features: DRAM ECC, memory mirroring, patrol scrub, MCA
- Exposure to PCIe Gen 5 or CXL 2.0/3.0 interconnect validation
- Hands-on experience with JEDEC DDR5 compliance testing and memory timing optimization
- Understanding of power management frameworks: ACPI, AMD STAPM, Intel DPTF, and platform telemetry
- Prior collaboration with silicon vendors on pre-silicon bring-up
- Experience with Git, CI/CD pipelines, and agile engineering workflows
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