Staff ASIC Design Engineer
On-site · Hyderabad, Telangana, India
Job Summary
Staff ASIC Design Engineer in Hyderabad leads RTL design and micro-architecture efforts for SoC blocks, drives synthesis, timing closure, and power optimization; collaborates with firmware, software, design verification, FPGA, DFT, and backend teams; supports prototyping, test programs, and chip validation from bring-up through production; conducts design bring-up and debugging on FPGA-based emulation; implements/analyses assertions and coverage metrics; works with PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI interfaces; mentors junior engineers, and uses scripting for automation; requires 7+ years RTL/verification/synthesis/timing experience, Verilog RTL coding, and strong SoC integration knowledge; experience with FPGA emulation platforms, tape-out cycles, and cross-functional collaboration; preferred: silicon bring-up on hardware and mentoring/leadership in design teams.
Required Qualifications
- 7+ years hands-on RTL logic design, verification, synthesis, and timing optimization
- Efficient, synthesizable RTL code in Verilog with SoC integration knowledge
- Micro-architecture design and translating specifications into implementations
- Experience with PCIe, USB, Ethernet, DDR/LPDDR4/5, I2C/I3C, eSPI, SPI
- FPGA-based emulation platforms (HAPS, Veloce) for design validation and debugging
- Scripting languages (Perl, Python) for automation
- Repository management tools (Bitbucket) and bug tracking systems (JIRA)
- Successful completion of at least one full tape-out cycle from design through silicon validation
- Strong communication and documentation skills
- Collaborative cross-functional work experience
- Preferred: Silicon bring-up on actual hardware
- Preferred: mentoring or leading junior design engineers
- Preferred: familiarity with design methodologies and industry best practices
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