Staff Analog Design Engineer, TX/RX Datapath
$155,000–$250,000 year
RemoteUnited States or Santa Clara, Villa Clara Province, Cuba
Job Summary
Own transistor-level design of the SerDes transmit path and receive front-end, including output drivers, pre-drivers, serializers, termination, ESD-aware inputs, CTLE, VGA, and samplers. Design and verify the equalization path covering DFE and FFE architecture, tap resolution, and adaptation behavior, while deriving block-level specifications from link budgets and defending them in design reviews. Build verification environments with testbenches, PVT corner coverage, Monte Carlo analysis, and post-layout simulation, providing behavioral and Verilog-A models for full-chip verification. Perform link and channel modeling using MATLAB or Python to analyze S-parameters, statistical eyes, and BER, then drive layout in deep sub-micron nodes and co-design with package and signal-integrity engineers. Take blocks through silicon bring-up and bench characterization, correlating measured performance against simulation.
Required Qualifications
- BS/MS/PhD in Electrical Engineering
- 8+ years of hands-on analog and mixed-signal circuit design experience
- Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link
- Deep knowledge of high-speed driver design, receive front-end design, and equalization
- Practical familiarity with the adjacent clocking and CDR blocks your datapath interfaces with
- Practical command of jitter and noise analysis — decomposition, budgeting, and the simulation methodology to quantify each contributor
- Circuit design experience in advanced FinFET or GAA process nodes
- Hands-on use of industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation)
- Link/channel modeling experience (e.g., MATLAB, Python, S-parameter models)
- Silicon bring-up and bench debug experience with high-speed lab equipment such as scopes and BERTs
- The judgment to distinguish a design problem from a measurement problem
Desired Qualifications
- Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including the specific constraints of short-reach, low-energy-per-bit links
- PAM4 signaling and DSP-based receiver architectures, including ADC-based front-ends
- Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7
- Experience porting a datapath block across process nodes, with a realistic sense of what that effort actually costs
- IBIS-AMI model generation
- SerDes ATE and production test development
- Participation in or contribution to standards bodies
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