Staff Analog Design Engineer, SerDes Clocking
$155,000–$250,000 year
RemoteUnited States or Santa Clara, Villa Clara Province, Cuba
Job Summary
Own transistor-level design of low-jitter frequency synthesis, including LC and ring PLLs, phase interpolators, and high-frequency clock distribution across the SerDes macro. Define and verify CDR architecture and loop dynamics by modeling behavior in MATLAB or Python, then build verification environments for PSS, transient noise, and Monte Carlo analysis. Drive layout in deep sub-micron nodes and lead silicon bring-up, correlating bench characterization results against simulation. This hands-on role spans specification through silicon characterization for d-Matrix's high-speed SerDes IO chiplet, partnering with datapath and DSP teams to close timing and jitter budgets.
Required Qualifications
- BS/MS/PhD in Electrical Engineering
- 5+ years of hands-on analog and mixed-signal circuit design experience
- Demonstrated ownership of a low-jitter PLL, phase interpolator, or CDR loop through silicon in a high-speed SerDes link
- Deep knowledge of PLL architecture, loop dynamics, VCO design, and phase noise theory
- Working knowledge of CDR architectures and the loop analysis behind jitter tolerance and jitter transfer
- Practical experience with jitter decomposition and budgeting methodology, including quantifying contributors in simulation
- Circuit design experience in advanced FinFET or GAA process nodes
- Experience using industry-standard analog design and simulation tools and methodologies (e.g., Cadence Virtuoso, Spectre, Monte Carlo/corner analysis, post-layout simulation)
- Silicon bring-up and bench debug experience with lab equipment such as phase noise analyzers, high-speed scopes, and BERTs
Desired Qualifications
- Die-to-die interconnect experience — UCIe, BoW, or a proprietary D2D PHY — including clocking architecture choices specific to short-reach, low-energy-per-bit links
- Forwarded-clock and matched-source-synchronous architectures alongside embedded-clock CDR
- Digital and hybrid PLL/CDR implementations, including the digital calibration around them
- Familiarity with relevant specifications: UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7
- Experience porting a clocking block across process nodes, with a realistic sense of what that effort costs
- Participation in or contribution to standards bodies
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