Staff Analog Design Engineer

Lead the design and development of high-performance analog power management ICs, ensuring best-in-class efficiency, power density, and reliability. Define product architecture with system engineers, select and implement optimal circuit topologies, perform transistor-level design and validation, and collaborate with layout teams to optimize silicon performance. Engage with global design teams to align on strategies and execution, and partner with test/characterization teams to define validation methodologies and production test strategies. This hybrid role requires onsite presence multiple days a week at either Richardson, TX or San Jose, CA offices. Required qualifications include a Bachelor’s degree in Electrical Engineering, 8+ years in semiconductor engineering, 6+ years in analog/mixed-signal IC design (DC-DC architectures and control methods), proficiency with EDA tools, and production-release experience. Preferred qualifications include a Masters or PhD in Electrical Engineering and experience with Cadence Virtuoso, Simplis, and ADS. Salary range provided: $144,300 – $187,600, California Bay Area context. The role emphasizes leadership in architecture, design, validation, cross-functional collaboration, and delivery of high-performance power management solutions.