Sr. Staff Engineer, Full-chip Physical Verification and Foundry Sign Off
On-siteBengaluru, Karnataka, India
Job Summary
Own full-chip physical-verification methodology, execution, closure, and final tapeout certification for complex mixed-signal SoCs. Drive DRC, LVS, ERC, PERC, antenna, density, DFM, metal-fill, XOR, and connectivity closure while developing hierarchical and incremental PV flows. Resolve complex LVS issues involving hierarchy, black boxes, analog/custom blocks, multiple power domains, global nets, CDL/SPICE netlists, and parameterized devices. Qualify foundry rule decks, runsets, tool versions, PDK updates, and signoff configurations. Establish processes for violation classification, ownership, review, waiver approval, and foundry disposition. Coordinate metal-fill generation, post-fill timing, extraction, EMIR, DRC, LVS, and density rechecks. Maintain auditable signoff checklists, dashboards, release criteria, database checksums, and tapeout-quality gates. Own final GDS/OASIS stream-out verification and foundry handoff. Work directly with physical design, analog layout, DFT, package, reliability, foundry, EDA, and external ASIC service teams. Automate repetitive PV analysis, reporting, triage, and regression activities. Mentor engineers and establish consistent PV practices across blocks and projects.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of ASIC physical verification or physical design experience
- Demonstrated full-chip PV ownership on at least three successful tapeouts
- Hands-on experience with N3/N3P or comparable leading-edge process nodes
- Mastery of Siemens Calibre nmDRC/nmLVS and experience with Cadence Pegasus or Synopsys ICV
- Deep knowledge of DRC, LVS, ERC, PERC, antenna, density, metal-fill, DFM, and XOR methodologies
- Experience debugging hierarchical, mixed-signal, multi-voltage, and top-level LVS problems
- Strong knowledge of LEF, DEF, GDSII, OASIS, CDL, SPICE, Verilog netlists, and layout connectivity
- Proficiency in Tcl, Python, Perl, shell, or SVRF-based automation
- Experience working directly with foundry rule decks, technical support, and waiver processes
Desired Qualifications
- Experience with custom analog, high-speed SerDes, photonics-interface, or mixed-signal SoCs
- Experience verifying bump maps, RDL, interposers, 2.5D/3DIC assemblies, and package connectivity
- Experience with ESD, latch-up, reliability, and current-density verification
- Experience developing or qualifying foundry signoff decks and flows
- Experience coordinating tapeouts through external ASIC service providers
- Experience debugging silicon issues traced to layout, connectivity, fill, or physical-verification escapes
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