Sr. Staff Engineer, EMIR/Power Integrity
On-siteBengaluru, Karnataka, India
Job Summary
Own full-chip static and dynamic IR-drop, electromigration, and power-integrity analysis from early floorplanning through final tapeout. Define EMIR signoff methodology, scenario coverage, guardbands, acceptance criteria, and waiver processes. Develop power-delivery strategies including power-domain planning, grid architecture, bump assignment, and decap allocation. Perform vectorless and vector-based dynamic voltage-drop analysis using realistic activity models. Incorporate package, interposer, and bump parasitic models into chip-level analysis. Sign off power and ground grids, critical current paths, and high-current analog interfaces. Identify risks early and drive corrective actions with physical-design, circuit-design, and package teams. Establish measurable voltage-drop, current-density, and reliability budgets. Develop dashboards communicating convergence and tapeout readiness. Build scalable hierarchical EMIR methodologies and automation flows. Qualify analysis models and foundry technology files. Work directly with foundries, EDA vendors, and external ASIC service providers to resolve technical issues. Mentor physical-design engineers and establish repeatable power-integrity practices across the organization.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or a related field
- 8+ years of experience in ASIC physical design, power integrity, or EMIR analysis
- Proven ownership of full-chip EMIR closure and signoff on successful advanced-node SoC tapeouts
- Strong hands-on experience with Ansys RedHawk-SC, Cadence Voltus, or equivalent industry-standard power-integrity tools
- Experience with advanced FinFET process technologies
- Deep understanding of power-distribution networks, static and dynamic voltage drop, electromigration, current-density limits, decap strategy, power gating, and package interactions
- Experience developing realistic current and activity models for vectorless and vector-based analysis
- Experience analyzing complex SoCs containing high-speed digital, custom analog/mixed-signal, memory, and clocking components
- Strong knowledge of physical-design implementation, including floorplanning, power planning, placement, clocking, routing, and signoff extraction
- Experience with extraction and power-analysis tools such as StarRC, Quantus, PrimePower, Joules, or equivalent
- Working knowledge of multi-voltage designs, UPF, power switches, always-on domains, and low-power implementation
- Proficiency in Tcl, Python, Perl, shell, or other scripting and automation languages
- Demonstrated ability to communicate technical risks clearly and drive closure across teams without relying on direct reporting authority
Desired Qualifications
- Experience with TSMC N3/N3P technology and associated EMIR signoff requirements
- Experience with co-packaged optics, silicon photonics, high-speed SerDes, UCIe, HBM, or other high-bandwidth interfaces
- Experience with 2.5D/3DIC systems, chiplets, interposers, RDL, and package-aware power-integrity analysis
- Experience with package-model generation, chip-package power-delivery co-design, and bump-current optimization
- Understanding of electrothermal analysis, self-heating, aging, reliability, and temperature-dependent electromigration
- Experience correlating pre-layout estimates, implementation analysis, signoff results, and post-silicon measurements
- Experience debugging silicon power-integrity, voltage-droop, or reliability issues
- Experience working directly with leading-edge foundries, OSATs, EDA vendors, and external ASIC service providers
- hands-on N5 or N3-class experience
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