Sr. Staff Engineer, ASIC Verification
On-site · Bengaluru, Karnataka, India
Job Summary
Lead verification strategy for Ayar Labs' next-generation silicon photonic chip. Architect scalable UVM testbench environments for complex IP blocks and subsystems, define verification methodologies and coverage metrics, and drive high-quality tape-out from concept. Collaborate with Architects and RTL Designers early in the cycle to define the verification plan, debug across RTL, firmware, and the verification environment, and mentor a team of engineers. Develop automation to streamline regression testing, performance analysis, and coverage closure; evaluate and deploy new EDA tools, formal verification techniques, or emulation flows. The role requires strong technical leadership, hands-on verification of multi-clock-domain digital designs, and experience with SerDes, memory interfaces (HBM), and related protocols, with a focus on end-to-end system verification from blocks to silicon.
Required Qualifications
- MS in Electrical Engineering, Computer Engineering, or related field with 6+ years of relevant experience in ASIC/SoC verification
- Expert-level proficiency in SystemVerilog and UVM (Universal Verification Methodology)
- Proven track record of building verification environments from scratch (Agents, Scoreboards, Sequencers, etc.)
- Deep knowledge of standard interface protocols (PCIe, ARM MCU, AMBA/AXI, UCIe)
- Strong proficiency in scripting languages for automation (Python, Perl, Tcl, or Shell)
- Experience defining functional coverage groups and driving logic verification to 100% closure
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