Sr. Staff Engineer, ASIC Physical Design
On-site · Bengaluru, Karnataka, India
Job Summary
Lead end-to-end ASIC physical design for blocks containing digital and custom analog/mixed-signal IP; responsible for synthesis, place-and-route, timing closure, STA, and physical verification (DRC/LVS) of mixed-signal SoCs. Drive DFT methodologies and automated design flows while coordinating across multiple designers. Candidate should have BS/MS in Electrical/Computer Engineering with 5+ years in ASIC physical design, Proficient in Verilog RTL and toolchains (Genus, Design Compiler, Encounter, Innovus, ICC), timing constraints, and STA. Preferred familiarity with Cadence Virtuoso, Python, 3DIC approaches, SerDes, and collaboration with external ASIC services. Location: Bengaluru, India; on-site with flexible hours.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 5+ years of work experience in ASIC physical design
- History of leading successful block implementations integrating custom IP in leading edge process nodes
- Proficient in Verilog RTL
- Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS) tools and flows
- Mastery of timing constraints and deep understanding of static timing analysis
- Proficient in clock tree synthesis methodologies and customization
- Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Proficient in ASIC signoff methodologies, checklists, and requirements
- Proficient in scripting or programming languages
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