Sr. Staff Engineer, ASIC Design
$180,000–$223,000 year
On-site · San Jose, California, United States
Job Summary
Senior Staff Engineer, ASIC Design responsibilities include designing, bringing up, and debugging complex digital subsystems within an electro-optical digital SoC. The role requires hands-on RTL/verification work in Verilog/SystemVerilog, development of testbenches and models, documentation for backend ASIC engineers, and collaboration with analog, photonics, and firmware teams. The candidate will perform bring-up and debug of in-house custom silicon, contribute to automated design methodologies, and work with high-speed interconnects and optical systems. Preferred qualifications include MS in related fields, experience with synthesis tools, timing analysis, LEF/lib integration, silicon bring-up, FPGA/microcontroller familiarity, Cadence Virtuoso, and DFT techniques.
Required Qualifications
- BS in Electrical Engineering, Computer Engineering, or related fields
- 5+ years of work or academic experience in ASIC design
- Mastery of Verilog and SystemVerilog for both RTL design and verification
- Proficient in ASIC verification (XCelium, VCS, Questa) tools
- Proficient in low-level programming languages (C, C++)
- Proficient in Python
- Working knowledge of digital timing constraints and ASIC tool flows
- Experience working on digital designs with multiple clock domains and clock dividers
- Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)
- Some knowledge of optics and control systems
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