Sr. Staff Engineer, ASIC Design
On-site · Bengaluru, Karnataka, India
Job Summary
Sr. Staff Engineer, ASIC Design in Bangalore focusing on design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC. Develop and optimize RTL in Verilog/SystemVerilog, create models and testbenches for digital/mixed-signal blocks, document designs for backend ASIC engineers, and perform bringup/evaluation of in-house custom silicon using Python scripting and control systems. Collaboration across analog, photonics, and firmware engineers; contribute to automated design methodologies and flows; work with high-speed interconnects and optical systems.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 5+ years of work or academic experience in ASIC design
- History of assuming responsibility for a variety of technical tasks and completing projects independently
- Mastery of Verilog and SystemVerilog for both RTL design and verification
- Proficient in ASIC verification (XCelium, VCS, Questa) tools
- Proficient in low-level programming languages (C, C++)
- Proficient in Python
- Working knowledge of digital timing constraints and ASIC tool flows
- Experience working on digital designs with multiple clock domains and clock dividers
- Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB)
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